It is often useful to combine multiple microelectronic devices, such as semiconductor die carrying integrated circuits (ICs), microelectromechanical systems (MEMS), optical devices, passive electronic components, and the like, into a single package that is both compact and structurally robust. Packaging of microelectronic devices has traditionally been carried-out utilizing a so-called two dimensional (2D) or non-stacked approach in which two or more microelectronic devices are positioned and interconnected in a side-by-side or laterally adjacent spatial relationship. More particularly, in the case of ICs formed on semiconductor die, packaging has commonly entailed the mounting of multiple die to a package substrate and formation of the desired electrical connections through wire bonding or flip-chip (FC) connections. The 2D microelectronic package may then later be incorporated into a larger electronic system by mounting the package substrate to a printed circuit board (PCB) or other component included within the electronic system.
As an alternative to 2D packaging technologies of the type described above, three dimensional (3D) packaging technologies have recently been developed in which microelectronic devices are disposed in a stacked arrangement and vertically interconnected to produce a stacked, 3D microelectronic package. Such 3D packaging techniques yield highly compact microelectronic packages well-suited for usage within mobile phones, digital cameras, digital music players, and other compact electronic devices. Additionally, such 3D packaging techniques enhance device performance by reducing interconnection length, and thus signal delay, between the packaged microelectronic devices. Considerable efforts have been expended in the development of so-called “Package-on-Package” or, more simply, “PoP” packaging technologies. In a conventional PoP packaging approach, vertical interconnection of the stacked microelectronic devices is performed on a package level. That is, subsequent to singulation into individual die via wafer dicing, the semiconductor die are encapsulated to produce a number of discrete die packages. The die packages (also referred to as “package layers” when included within a PoP package) are then stacked and vertically interconnected to produce the completed PoP package. Emerging PoP technologies include Wire Bond (WB) Ball Grid Array (BGA) PoP, FC PoP, Thru Mold Via (TMV) FC PoP, and Redistributed Chip Package (RCP) PoP packaging approaches.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.